In the existing memory system, cache memories have a hierarchical structure and data which is frequently accessed is stored in a high-speed low-order cache memory. In this way, the memory access speed of the processor increases.
However, in recent years, generally, a plurality of processor cores have been provided to perform processes in parallel. When the processor cores access the cache memory in parallel, there is a concern that a cache miss is likely to occur in the existing hierarchical cache memories.
In many cases, a high-speed volatile memory, such as an SRAM, is used as the cache memory. The power consumption of the SRAM is more than that of a DRAM which is generally used as a main memory. In addition, since the SRAM is a volatile memory, power is required to maintain data even in a standby state in which the SRAM is not accessed.